Peer-Reviewed Journal Details
Mandatory Fields
Keller M., Ronan R., Marnane W.P., Murphy, C.C.
2007
September
Computers and Electrical Engineering
Hardware Architectures for the Tate Pairing over GF(2^m)
Published
()
Optional Fields
Tate pairing Cryptography Hardware architecture BKLS/GHS algorithm
33
5-6
392
406
In this paper two different approaches to the design of a reconfigurable Tate pairing hardware accelerator are presented. The first uses macro components based on a large, fixed number of underlying Galois Field arithmetic units in parallel to minimise the computation time. The second is an area efficient approach based on a small, variable number of underlying components. Both architectures are prototyped on an FPGA. Timing results for each architecture with various different design parameters are presented.
0045-7906
10.1016/j.compeleceng.2007.05.002
Grant Details
Irish Research Council for Science Engineering and Technology (RS/2004/67)