The dominant cost in Elliptic Curve Cryptography (ECC) over prime fields is modular multiplication. Minimal Redundancy Cyclotomic Primes (MRCPs) were recently introduced by Granger et al. for use as base field moduli in ECC, since they permit a novel and very efficient modular multiplication algorithm. Here we consider a reconfigurable hardware implementation of arithmetic modulo a 258-bit example, for use at the 128-bit AES security level. We examine this implementation for speed and area using parallelisation methods and inbuilt FPGA resources. The results are compared against a current method in use, the Montgomery multiplier.