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Mandatory Fields
Cummins, C.; Gangnaik, A.; Kelly, R. A.; Hydes, A. J.; O’Connell, J.; Petkov, N.; Georgiev, Y. M.; Borah, D.; Holmes, J. D.; Morris, M. A.
Chemistry of Materials
Parallel arrays of sub-10 nm aligned germanium nanofins from an in-situ metal oxide hardmask using directed self-assembly of block copolymers
WOS: 16 ()
Optional Fields
High-mobility materials and non-traditional device architectures are of key interest in the semiconductor industry because of the need to achieve higher computing speed and low power consumption. In this article, we present an integrated approach using directed self-assembly (DSA) of block copolymers (BCPs) to form aligned line-space features through graphoepitaxy on germanium on insulator (GeOI) substrates. Ge is an example of a high mobility material (III−V, II−VI) where the chemical activity of the surface and its composition sensitivity to etch processing offers considerable challenges in fabrication compared to silicon (Si). We believe the methods described here afford an opportunity to develop ultrasmall dimension patterns from these important high-mobility materials. High-quality metal oxide enhanced pattern transfer to Ge is demonstrated for the realization of nanofins with sub-10 nm feature size. Graphoepitaxial alignment of a poly(styrene)-blockpoly(4-vinylpyridine) (PS-b-P4VP) BCP was achieved using predefined hydrogen silsesquioxane (HSQ) topography at a GeOI substrate. Subsequent impregnation of the aligned BCP templates with a salt precursor in situ and simple processing was used to generate robust metal oxide nanowire (e.g., Fe3O4, γ-Al2O3, and HfO2) hardmask arrays. Optimized plasma based dry etching of the oxide modified substrate allowed the formation of high aspect ratio Ge nanofin features within the HSQ topographical structure. We believe the methodology developed has significant potential for high-resolution device patterning of high mobility semiconductors. We envision that the aligned Ge nanofin arrays prepared here via graphoepitaxy might have application as a replacement channel material for complementary metal−oxide−semiconductor (CMOS) devices and integrated circuit (IC) technology. Furthermore, the low capital required to produce Ge nanostructures with DSA technology may be an attractive route to address technological and economic challenges facing the nanoelectronic and semiconductor industry.
Washington DC, USA
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