Peer-Reviewed Journal Details
Mandatory Fields
Bellis, S. J.; Marnane, W.P.; Larsson-Edefors, P.;
1999
International Journal of Electronics
Bit Serial, MSB First Processing Units
Published
()
Optional Fields
86
6
723
738
This paper introduces three new bit-serial designs for the arithmetic operations of division, square-root and multiplication. The designs are novel in that they adopt the same 2ís complement number system, operate on amost significant bit first data stream and use a data interleaving scheme to achieve high throughput. The communication of data between the designs is streamlined, with a minimum of control and conversion circuitry required. This allows the architectures to be used in conjunction with high speed analogue-to-digital conversion techniques such as pipelined ADCs and successive approximation ADCs. These high speed ADCs are required in complex DSP algorithms such as parametric spectral estimation, where the three arithmetic functions of multiplication, division and square-root are also required.
0020-7217
10.1080/002072199133184
Grant Details