Peer-Reviewed Journal Details
Mandatory Fields
Marnane W. P., Moore W. R.
1995
April
Journal of Electronic Testing, Theory and Application
Test Pattern Generation for VSLI Regular Arrays
Published
Scopus: 2 ()
Optional Fields
testing regular arrays test vector generation C-testability
6
2
153
177
In recent years the concept of 'Design for Test' whereby the designer is forced to comply with a specific test style-has become very popular. However, the most effective custom VLSI architectures available all have their own very strongly defined structure. Therefore, test strategies are required which exploit the typical hierarchy in the design. Exploiting this hierarchy implies a test philosophy which requires the minimum addition of extra test logic and utilizes the hierarchy of the design. A popular VLSI architecture is a systolic array which consists of a regular array of small processing elements with timing latches on the communication lines. In this case we can exploit the regularity for test purposes; in this paper we show how to do this by adopting a divide and conquer
method. This can be done by generating test vectors for a single processing element, using the most appropriate fault model. The regularity of the array facilitates the propagation of these vectors to every other processing element in the array. The propagation method must also allow for the propagation of the fault effects from the output of each processing element to the boundary of the array where the fault can be observed. The proposed test method presented in this paper takes the vectors required to test a single processing element, and determines test vectors for the whole array. This method is applicable to all types of regular arrays, but in particular, systolic arrays,
where we have the added problem of circuit timing. Each separate signal direction is first analyzed for its test vector and fault effect propagation properties. Then, using the array Data Dependence Graph, which represents the propagation of data through the array, the combined effect of all signals on test vector and fault effect propagation
can be considered. This reduces the task of determining the array inputs to a pattern matching problem suitable for computer implementation. The test method is applied to three different arrays to illustrate how different array types can be tested.
0923-8174
10.1007/BF00993084
Grant Details