Peer-Reviewed Journal Details
Mandatory Fields
Marnane W. P., Bellis S. J., Larsson-Edefors P.
1997
June
Electronic Letters
Bit Serial Interleaved High Speed Division
Published
()
Optional Fields
33
13
1124
1125
A bit-serial word-parallel divider circuit with simplified control requirements, is presented. The circuit uses the non-restoring division algorithm which places a restriction on the speed of the circuit. By introducing the concept of bit interleaving, a high speed design can be implementcd of the same circuit complexity as an equivalent size multiplier.
UK
0013-5194
10.1049/el:19970758
Grant Details