Palser, K;Concannon, A;Duffy, R;Mathewson, A

1999

May

Microelectronics Reliability

Analysis of external latch-up protection test structure design using numerical simulation

Validated

WOS: 3 ()

39

647

659

With each new CMOS technology the latch-up sensitivity and effects of prevention strategies change. Products built in these technologies must adhere to stringent guidelines for latch-up 'Hardness', and for this reason characterisation of new technologies is needed through the use of test structures. This paper shows a numerical simulation approach which can determine the relative effectiveness of guard-rings in ESD protection device test structures. In this work. time taken to characterise latch-up protection test structures and to chose a protection strategy is greatly reduced by using numerical simulations to design the test structures. The results presented are for variations to the guard-rings for two technologies. Included in these are the typical simulation times and resources required. The technique outlined has the joint advantages of providing accurately representative simulations of the technology and test structure layout in a practical time frame. (C) 1999 Elsevier Science Ltd. All rights reserved.

OXFORD

0026-2714