Lovett, SJ;Welten, M;Mathewson, A;Mason, B

1998

January

IEEE Journal of Solid-State Circuits

Optimizing MOS transistor mismatch

Validated

WOS: 43 ()

33

147

150

An investigation of MOS transistor mismatch is undertaken and a methodology is developed for optimizing mis-match without increasing layout area. Dramatic improvements of up to 300% in matching can be realized by selecting the optimum W/L ratio without changing the overall WL area product, The theoretical basis for the obtainable improvements is fully described and an expression is derived and verified by experiment to predict the W/L ratio which gives optimum matching.

PISCATAWAY

0018-9200