Peer-Reviewed Journal Details
Mandatory Fields
Kerins T., Marnane W. P., Popovici E. M., Baretto P.S.L.M
2005
October
IEE Proceedings - Information Security
Hardware Accelerators for Pairing based Cryptosystems
Published
()
Optional Fields
152
1
47
56
Polynomial basis hardware architectures are described for the mathematical operations required in pairing based cryptosystems in characteristic p=3. In hardware, arithmetic operations in extension fields of GF(3^m) can be parallelised, and this results in high performance dedicated processors for efficient Tate pairing calculation. The implementation
aspects of two such hardware processors are discussed through prototyping over GF(3^97) on the Xilinx Virtex2 and Virtex2Pro FPGA technologies.
1747-0722
10.1049/ip-ifs: 20055009
Grant Details
Enterprise Ireland