Conference Publication Details
Mandatory Fields
Marnane W. P.; Moore W. R.; Gautrin E;
International Workshop on Designing for Yield, edited priceedings: Yield Modeling and Defect Tolerance in VLSI published by Adam HilgerISBN 0-85274-398-X
Structured Test of Bit-Level Systolic Arrays
1987
July
Published
1
()
Optional Fields
Moore W. R., Maly W., Strojwas A.
261
271
Oxford, UK.
01-JUL-87
03-JUL-87
*
Grant Details