Keller M.; Kerins T.; Marnane W. P.;

IEEE Intrnational Conference on Programmable Logic and Applications (FPL 2005)

FPGA Implementation of a GF(2^(4m)) Multiplier for use in a Pairing Based Cryptosystem

2005

August

Published

1

Scopus: 7 ()

594

597

Tampere, Finland

24-AUG-05

26-AUG-05

In this paper an architecture for GF(2^4m) multiplication is outlined. It is illustrated how this operation is critical to efficient hardware implementation of the Tale pairing, which itself is the underlying calculation in many new pairing based cryptosystems. Tate pairing calculation times using an FPGA hardware accelerator are estimated based on results from the multiplier architecture.

10.1109/FPL.2005.1515793