Peer-Reviewed Journal Details
Mandatory Fields
Marnane, WP
1998
April
Electronics Letters
Optimised bit serial modular multiplier for implementation on field programmable gate arrays
Validated
WOS: 5 ()
Optional Fields
34
738
739
A high-speed architecture for bit serial modular multiplication is presented. The design of this array is highly regular, allowing the specific logic and routing resources available in field programmable gate arrays (FPGAs) to be exploited. Furthermore, an optimised array is presented which exploits the reprogrammability of the FPGA, such that a longer bit length can be implemented on the same FPGA.
HERTFORD
0013-5194
Grant Details