Peer-Reviewed Journal Details
Mandatory Fields
Bellis, SJ;Marnane, WP;Larsson-Edefors, P
1999
June
International Journal of Electronics
Bit-serial, MSB first processing units
Validated
()
Optional Fields
A/D CONVERTER ARCHITECTURES MULTIPLIERS DESIGN CMOS
86
723
738
This paper introduces three new bit-serial designs for the arithmetic operations of division, square-root and multiplication. The designs are novel in that they adopt the same 2's complement number system, operate on a most significant bit first data stream and use a data interleaving scheme to achieve high throughput. The communication of data between the designs is streamlined, with a minimum of control and conversion circuitry required. This allows the architectures to be used in conjunction with high speed analogue-to-digital conversion techniques such as pipelined ADCs and successive approximation ADCs. These high speed ADCs are required in complex DSP algorithms such as parametric spectral estimation, where the three arithmetic functions of multiplication, division and square-root are also required.
LONDON
0020-7217
Grant Details