Peer-Reviewed Journal Details
Mandatory Fields
Spagnol, C., Popovici, E.M., Marnane, W.P.;
2009
September
IEEE Transactions On Circuits and Systems I-Regular Papers
Hardware Implementation of GF(2^m) LDPC Decoders
Validated
()
Optional Fields
FPGA galois fields low density parity check (LDPC) codes VLSI PARITY-CHECK CODES COMPLEXITY CHANNELS ARCHITECTURE CAPACITY BLOCK
56
12
2609
2620
Low density parity check (LDPC) codes over GF(2(m)) are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over GF(2(m)) codes. This paper proposes a novel variation of the belief propagation algorithm for GF(2(m)) LDPC codes. The new algorithm results in a reduced hardware complexity when implemented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over GF(2(m)) are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over GF(2(m)) decoder is feasible for short to medium length codes. The additional complexity of the decoder is balanced by the superior performance of GF(2(m)) LDPC codes.
USA
1549-8328
DOI 10.1109/TCSI.2009.2016621
Grant Details
Irish Research Council for Science Engineering and Technology (RS/2004/144)