Conference Publication Details
Mandatory Fields
Djara V.;Cherkaoui K.;Thomas K.;Pelucchi E.;O'Connell D.;Floyd L.;Hurley P.
2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011
Annealing investigations for high-k first n-channel In 0.53Ga0.47As MOSFET development
2011
June
Validated
1
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Optional Fields
206
209
We present the development of a high-k first n-channel InGaAs metal-oxide-semiconductor field effect transistors (MOSFETs) and the effect of annealing on the source/drain (S/D) sheet resistance (Rs) and the high-k gate oxide. Test structures based on the transfer length method (TLM) were used as part of a design of experiment (DOE) to optimize the S/D implant activation process. The optimized process was 715C for 32 s, leading to a minimum Rs of (195.6 3.4) O/. Metal-oxide-semiconductor capacitors (MOSCAPs) with a 2 nm Al2O 3 / 8 nm HfO2 gate oxide were annealed at 675C, 700C and 725C for 30 s. Leakage current lower than 2.110 -8 A/cm2 were obtained for electric fields of ~3 MV/cm and low frequency dispersion of capacitance in accumulation (<1.7%) were obtained. Densities of interface states (DIT) were estimated using the conductance method. The output characteristics of a 5-m gate length MOSFET annealed at 650C is presented. 2011 IEEE.
10.1109/ULIS.2011.5758001
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