Introduction of dopant impurities in Si can be done in-situ during epitaxial growth, or ex-situ for localized material modification using a variety of sources including ion implantation, solid, liquid, or gas. In this work, we apply these methods for dopant incorporation and evaluate their effectiveness via electrical characterization. Moreover, it should be noted that evaluating doping processes entirely on planar Si surfaces can be misleading: processes which appear promising initially may not be transferrable to non-planar, thin-body structures like fins or nanowires, due to undesirable effects such as unwanted etching of the Si, and the difficulty in accessing all surfaces of extremely finely-spaced features. Arrays of Si nanowires, with diameters between 10 and 300 nm, and with inter-wire separations ranging from 20 to 1000 nm are fabricated by e-beam lithography, doped using the various methods, then measured electrically to evaluate the effectiveness of each method with respect to wire diameter and spacing. Calculated values for the material resistivity (accounting for contact resistance and wire geometry) are used to benchmark each process. Dopant incorporation was also evaluated on planar silicon-on-insulator (SOI) substrates of different Si thickness, ranging from 3 to 66 nm electrical characterization. These measurements show the influence of silicon thickness and drop-off of the electrical performance as SOI is scaled down towards its ultimate limit.