Peer-Reviewed Journal Details
Mandatory Fields
English, T,Popovici, E,Keller, M,Marnane, WP;
2011
January
Journal of Systems Architecture
Network-on-Chip interconnect for pairing-based cryptographic IP cores
Validated
()
Optional Fields
Interconnect Network-on-Chip Cryptography Tate Pairing GF(2(M)) NOC
57
1
95
108
On-chip data traffic in cryptographic circuits often consists of very long words or large groups of smaller words exchanged between processing elements. The resulting wide cross-chip buses exhibit power, congestion and scalability problems. In this paper, two case study cryptographic IP cores with demanding interconnect requirements are Implemented on 65 nm CMOS. Lightweight, custom bus-replacement Networks-on-Chip (NoCs) have been developed for both cores. Results show that eliminating the 251-bit-wide cross-chip cryptographic buses dramatically improves the quality of physical implementation. The results have applicability to wire-constrained designs in other domains.
1383-7621
DOI 10.1016/j.sysarc.2010.10.006
Grant Details