Other Publication Details
Mandatory Fields
Other
Byrne, A, Popovici, EM, O'Sullivan, M;
2005
May
Versatile Architectures For Decoding A Class of Ldpc Codes
Validated
1
()
Optional Fields
This paper presents a construction for low and high rate Low-Density Parity Check (LDPC) codes, their performance and efficient hardware implementation. The problem with decoding for LDPC codes is the linear increase in resource requirements as the size of the parity check matrix increases. This results in a number of issues with regard to practical implementation. These issues include interconnect routing, memory size and parallelism. A construction for low complexity, variable rate LDPC code will be introduced and an architecture that takes advantage of certain properties of this construction is proposed. A versatile LDPC decoding architecture is then evaluated on FPGA..
269
272
Grant Details